View HYS64D16000GDL-8-B_414762.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

D a t a S h e e t , V 1 . 2 , A u g . 2 00 3
H Y S 64 D 3 2 0 2 0 G D L - [ 5 / 6 / 7 / 8 ] - B H Y S 64 D 1 6 0 0 x G D L - [ 6 / 7 / 8 ] - B
200- Pi n Small Outli ne Dual -In- Line Memor y Modules S O -D I M M DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
Edition 2003-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , V 1 . 2 , A u g . 2 00 3
H Y S 64 D 3 2 0 2 0 G D L - [ 5 / 6 / 7 / 8 ] - B H Y S 64 D 1 6 0 0 x G D L - [ 6 / 7 / 8 ] - B
200- Pi n Small Outli ne Dual -In- Line Memor y Modules S O -D I M M DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
HYS64D32020GDL-[5/6/7/8]-B, HYS64D1600xGDL-[6/7/8]-B, Revision History: Previous Version: Page all 6,7,26,16 7 18 16,17 29 18 V1.2 V1.1 2003-08 2003-03
Subjects (major changes since last revision) New data sheet template Added Part number HYS64D32020GDL-5-B including SPD and IDD Updated Complinance Code Added DDR400B AC characteristics added Corrected IDD 256MB for speed sort -6 & -7 Updated Package Outlines Removed tbd from Table 11 for DDR400B tIPW & tDIPW
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.0_2003-06-06.fm
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Data Sheet
5
V1.2, 2003-08
200-Pin Small Outline Dual-In-Line Memory Modules SO-DIMM
HYS64D32020GDL-[5/6/7/8]-B HYS64D1600xGDL-[6/7/8]-B
1
1.1
* * * * * * * * * * * * *
Overview
Features
Non-parity 200-Pin Small Outline Dual-In-Line Memory Modules One rank 16M x 64 and two bank 32M x 64 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5 V ( 0.2 V) power supply Built with 256 Mbit DDR SDRAMs organised as x 16 in P-TSOPII-66-1 packages Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Serial Presence Detect with E2PROM Jedec standard form factor: 67.60 mm x 31.75 mm x 3.00 / 3.80 mm Jedec standard reference layout Raw Cards A and C DDR400 speed grade supported Gold plated contacts Performance -5 DDR400B -6 DDR333B 166 166 133 -7 DDR266A -- 143 133 -8 DDR200 -- 125 100 Unit -- MHz MHz MHz Component Module
Table 1
Part Number Speed Code Speed Grade
PC3200-3033 PC2700-2533 PC2100-2033 PC1600-2022 --
max. Clock Frequency @CL3
fCK3 200 @CL2.5 fCK2.5 166 @CL2 fCK2 133
1.2
Description
The HYS64D32020GDL-[5/6/7/8]-B and HYS64D1600xGDL-[6/7/8]-B are industry standard 200-Pin Small Outline Dual-In-Line Memory Modules (SO-DIMMs) organized as 32M x 64 and 16M x 64. The memory array is designed with Double Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Data Sheet
6
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Overview Table 2 Type PC3200 (CL=3) HYS64D32020GDL-5-B PC2700 (CL=2.5) HYS64D16000GDL-6-B HYS64D16001GDL-6-B HYS64D32020GDL-6-B PC2100 (CL=2) HYS64D16000GDL-7-B HYS64D16001GDL-7-B HYS64D32020GDL-7-B PC1600 (CL=2) HYS64D16000GDL-8-B HYS64D32020GDL-8-B Notes 1. All part numbers end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS64D32020GDL-6-B, indicating rev. B dies are used for SDRAM components. 2. The Compliance Code is printed on the module labels describing the speed sort (for example "PC2700"), the latencies and SPD code definition (for example "2033-0" means CAS latency of 2.0 clocks, RCD1) latency of 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module. PC1600S-2022-0-C1 PC1600S-2022-0-A1 one rank 128 MB SO-DIMM two ranks 256 MB SO-DIMM 256 MBit (x 16) 256 MBit (x 16) PC2100S-2033-0-C1 PC2100S-2033-0-C1 PC2100S-2033-0-A1 one rank 128 MB SO-DIMM one rank 128 MB SO-DIMM two ranks 256 MB SO-DIMM 256 MBit (x 16) 256 MBit (x 16) 256 MBit (x 16) PC2700S-2533-0-C1 PC2700S-2533-0-C1 PC2700S-2533-0-A1 one rank 128 MB SO-DIMM one rank 128 MB SO-DIMM two ranks 256 MB SO-DIMM 256 MBit (x 16) 256 MBit (x 16) 256 MBit (x 16) PC3200S-3033-0-A1 two ranks 256 MB SO-DIMM 256 Mbit (x 16) Ordering Information Compliance Code Description SDRAM Technology
1) RCD: Row-Column-Delay
Data Sheet
7
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Pin Configuration
2
Table 3 Symbol A0 - A12 BA0, BA1 DQ0 - DQ63
Pin Configuration
Pin Definitions and Functions Type1) I I I/O I I I/O I I I I PWR GND PWR PWR AI PWR I I/O I NC NU Function Address Inputs Bank Address Data Input/Output Command Input Clock Enable SDRAM Data Strobe SDRAM Clock (true signal) SDRAM Clock (complementary signal) Data Mask Chip Select Power (+ 2.5 V) Ground I/O Driver power supply VDD Indentification flag I/O reference supply Serial EEPROM power supply Serial bus clock Serial bus data line slave address select Not Connected Not Usable, reserved for future use
RAS, CAS, WE CKE0 - CKE1 DQS0 - DQS7 CK0 - CK1, CK0 - CK1 DM0 - DM8 S0, S1 VDD VSS VDDQ VDDID VREF VDDSPD SCL SDA SA0 - SA2 NC NU
2)
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not Connected; NU: Not Usable 2) CKE1 and S1 are used on two bank modules only
Table 4 Density 128MB 256MB
Address Format Organization 16M x 64 32M x 64 Memory Ranks 1 2 SDRAMs 16M x 16 16M x 16 # of SDRAMs 4 8 # of row/bank/ columns bits 13/2/9 13/2/9 Refresh 8K 8K Period 64 ms 64 ms Interval 7.8 s 7.8 s
Data Sheet
8
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Pin Configuration Table 5 Front side Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Symbol Pin Configuration Back side Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Key 41 43 45 47 49 51 53 55 57 59 61 63 DQ16 DQ17 42 44 46 48 50 52 54 56 58 60 62 64 DQ20 DQ21 Symbol Front side Pin # 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 Symbol DQ26 DQ27 Back side Pin # 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 Symbol DQ30 DQ31 Front side Pin # 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Symbol DQS4 DQ34 Back side Pin # 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Symbol DM4 DQ38
VREF VSS
DQ0 DQ1
VREF VSS
DQ4 DQ5
VDD
(CB0) (CB1)
VDD
(CB4) (CB5)
VSS
DQ35 DQ40
VSS
DQ39 DQ44
VDD
DQS0 DQ2
VDD
DM0 DQ6
VSS
(DQS8) (CB2)
VSS
(DM8) (CB6)
VDD
DQ41 DQS5
VDD
DQ45 DM5
VSS
DQ3 DQ8
VSS
DQ7 DQ12
VDD
(CB3) DU
VDD
(CB7) DU
VSS
DQ42 DQ43
VSS
DQ46 DQ47
VDD
DQ9 DQS1
VDD
DQ13 DM1
VSS
(CK2) (CK2)
VSS
DQ10 DQ11
VSS
DQ14 DQ15
VDD
CKE1 DU A12 A9
VSS VSS VDD VDD
CKE0 DU A11 A8
VDD VDD VSS VSS
DQ48 DQ49
VDD
CK1 CK1
VSS
DQ52 DQ53
VDD
CK0 CK0
VSS
VDD VDD VSS VSS
VDD
DQS6 DQ50
VDD
DM6 DQ54
VSS
A7 A5 A3 A1
VSS
A6 A4 A2 A0
VSS
DQ51 DQ56
VSS
DQ55 DQ60
VDD
DQ57 DQS7
VDD
DQ61 DM7
VDD
DQS2 DQ18
VDD
DM2 DQ22
VDD
A10/AP BA0 WE S0 DU
VDD
BA1 RAS CAS S1 DU
VSS
DQ58 DQ59
VSS
DQ62 DQ63
VSS
DQ19 DQ24
VSS
DQ23 DQ28
VDD
SDA SCL
VDD
SA0 SA1 SA2 DU
VDD
DQ25 DQS3
VDD
DQ29 DM3
VSS
DQ32 DQ33
VSS
DQ36 DQ37
VSS
VSS
VDD
VDD
VDDSPD VDDID
Data Sheet
9
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Pin Configuration
pin 40 pin 42
back side
Figure 1
Pin Configuration
Data Sheet
10
pin 200
pin 2
pin 199
pin 39 pin 41
front side
pin 1
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Pin Configuration
CS 0 CS DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DM5 D0 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 D2 CS
DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS
DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS
D1
D3
Unless otherwise noted, resistor values are 22 Ohm with +/- 5% tolerance Serial Presence Detect (SPD) BA0-BA1 A0-AN RAS CAS WE CKE0 CKE1 SDRAMS D0-D3 SDRAMS D0-D3 SDRAMS D0-D3 SDRAMS D0-D3 SDRAMS D0-D3 SDRAMS D0-D3 N.C. CK0 CK 0 V DD SPD V REF V DD V SS V DD ID SPD SDRAMS D0-D3 CK1 CK 1 Note: DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. V DD ID strap connections: Strap out (open): VDD = VDDQ 2 loads SCL SA0 SA1 SA2 A0 A1 A2 WP SDA
2 loads
SDRAMS D0-D3 V DD and V DD Q SDRAMS D0-D3, SPD
Figure 2
Block Diagram - One Rank 16M x 64 DDR SDRAM SO-DIMM HYS64D1600xGDL-[6/7/8]-B
Data Sheet
11
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Pin Configuration
CS1 CS0
CS CS
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4
CS
CS
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4
DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
DQS4 DM4
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM
D0
I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
D4
D2
I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
D6
DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS5 DM5
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
DQS2 DM2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
CS
LDQS
CS
LDQS
CS
CS
LDQS
LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 D1 I/O 6 I/O 7
UDQS
LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 D5 I/O 5 I/O 6 I/O 7
UDQS
DQS6 DM6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
LDQS
LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 D3 I/O 6 I/O 7
UDQS
LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
UDQS
D7
DQS3 DM3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
DQS7 DM7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
Serial Presence Detect (SPD)
SCL SA0 SA1 SA2 A0 A1 A2 WP SDA
Unless otherwise noted, resistor values are 22 Ohm with +/- 5% tolerance BA0-BA1 A0-AN RAS CAS WE CKE0 CKE1 V DD SPD V REF V DD V SS V DD ID SDRAMS D0-D7 SDRAMS D0-D7 SDRAMS D0-D7 SDRAMS D0-D7 SDRAMS D0-D7 SDRAMS D0-D3 SDRAMS D4-D7 SPD SDRAMS D0-D7 V DD and V DD Q Note: DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. V DD ID strap connections: Strap out (open): VDD = VDDQ SDRAMS D0-D7, SPD CK0 CK 0 CK1 CK 1 4 loads 4 loads
SDRAMS D0-D7
Figure 3
Block Diagram - Two Rank 32M x 64 DDR SDRAM SO-DIMM HYS64D32020GDL-[5/6/7/8]-B
Data Sheet
12
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Electrical Characteristics
3
3.1
Table 6 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol min. Values typ. - - - - - - 1 50 max. Unit Note/ Test Condition V V V V C C W mA - - - - - - - -
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT -0.5 VIN VDD VDDQ TA TSTG PD IOUT
-1 -1 -1 0 -55 - -
VDDQ +
0.5 +3.6 +3.6 +3.6 +70 +150 - -
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Table 7 Parameter Device Supply Voltage Electrical Characteristics and DC Operating Conditions Symbol Min. 2.3 2.5 2.3 2.5 2.3 0 0.49 x 0.5 x Values Typ. 2.5 2.6 2.5 2.6 2.5 Max. 2.7 2.7 2.7 2.7 3.6 0 0.51 x V V V V V V V Unit Note/Test Condition 1)
VDD Device Supply Voltage VDD Output Supply Voltage VDDQ Output Supply Voltage VDDQ EEPROM supply voltage VDDSPD Supply Voltage, I/O Supply VSS, Voltage VSSQ VREF Input Reference Voltage
I/O Termination Voltage (System)
fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3)
-- --
4)
VTT
VDDQ VDDQ VREF - 0.04 VREF + 0.15
-0.3 -0.3 0.36 0.71
VDDQ VREF + 0.04 V VDDQ + 0.3 V VREF - 0.15 V VDDQ + 0.3 V VDDQ + 0.6 V
1.4 --
5)
Input High (Logic1) Voltage VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current
8) 8) 8)
VIN(DC) VID(DC)
VIRatio
8)6)
7)
Data Sheet
13
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Electrical Characteristics Table 7 Parameter Input Leakage Current Electrical Characteristics and DC Operating Conditions (cont'd) Symbol Min. Values Typ. Max. 2 A Any input 0 V VIN VDD; All other pins not under test = 0 V 8)9) DQs are disabled; 0 V VOUT VDDQ 8) -2 Unit Note/Test Condition 1)
II
Output Leakage Current Output High Current, Normal Strength Driver Output Low Current, Normal Strength Driver
1) 0 C TA 70 C
IOZ IOH IOL
-5 -- 16.2
5 -16.2 --
A mA mA
VOUT = 1.95 V 8) VOUT = 0.35 V 8)
2) DDR400 conditions apply for all clock frequencies above 166 MHz 3) Under all conditions, VDDQ must be less than or equal to VDD. 4) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 6) VID is the magnitude of the difference between the input level on CK and the input level on CK. 7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) Inputs are not recognized as valid until VREF stabilizes. 9) Values are shown per DDR SDRAM component
Data Sheet
14
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Electrical Characteristics
3.2
Table 8 Parameter
Current Specification and Conditions
IDD Conditions
Symbol
Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIH,MIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, burst refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet.
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
Data Sheet
15
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Electrical Characteristics
Table 9
IDD Specification HYS64D16000GDL-6-B HYS64D16001GDL-6-B HYS64D32020GDL-6-B HYS64D32020GDL-5-B Unit Note1)2)
Part Number & Organization
128MB x 64 1 Rank -6 typ. 352 416 24 180 99 72 252 496 564 574 5 872 max. 460 500 36 220 112 84 280 640 660 760 5 1140
256MB x 64 2 Ranks -6 typ. 604 668 48 360 198 144 504 748 816 826 10 1280 max. 740 780 72 440 224 168 560 920 940 1040 10 1536
256MB x 64 2 Ranks -5 typ. 640 700 48 368 192 136 480 800 840 860 10 1280 max. 776 836 72 448 272 192 592 996 1016 1076 10 1536 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
16
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Electrical Characteristics
Table 10
IDD Specification HYS64D16000GDL-8-B HYS64D32020GDL-8-B HYS64D16000GDL-7-B HYS64D16001GDL-7-B HYS64D32020GDL-7-B Unit Note1)2)
Part Number & Organization
128MB x 64 1 Rank -8 typ. 288 332 20 120 72 52 168 356 384 504.8 6 632 max. 380 420 28 140 88 64 200 440 480 680 6 880
256MB x 64 2 Ranks -8 typ. 456 500 40 240 144 104 336 524 552 672.8 12 800 max. 580 620 56 280 176 128 400 640 680 880 12 1080
128MB x 64 1 Rank -7 typ. 308 376 22 140 376 60 208 428 476 540 6 720 max. 420 460 32 160 100 72 240 520 560 720 6 940
256MB x 64 2 Ranks -7 typ. 516 584 44 280 752 120 416 636 684 748 12 928 max. 660 700 64 320 200 144 480 760 800 960 12 1180 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
17
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
AC Characteristics
4
Table 11 Parameter
AC Characteristics
AC Timing - Absolute Specifications -6/-5 Symbol Min. -6 DDR333 Max. +0.7 +0.6 0.55 0.55 12 12 12 -- -- -- -- +0.7 +0.7 1.25 +0.45 +0.55 -- -- -- -- -- -- 0.60 -- Min. -0.6 -0.5 0.45 0.45 5 6 7.5 0.4 0.4 2.2 1.75 -0.6 -0.6 0.75 -- -- -5 DDR400B Max. +0.6 +0.5 0.55 0.55 12 12 12 -- -- -- -- +0.6 +0.6 1.25 +0.40 +0.50 -- -- -- -- -- -- 0.60 -- ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Unit
Note/ Test Condition 1)
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time
tAC tDQSCK tCH tCL tHP tCK
-0.7 -0.6 0.45 0.45 6 6 7.5
tCK tCK
ns ns ns ns ns ns ns ns ns ns
min. (tCL, tCH)
min. (tCL, tCH)
CL = 3.0
2)3)4)5)
CL = 2.5
2)3)4)5)
CL = 2.0
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)6)
DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK
tDH tDS tIPW tDIPW tHZ
0.45 0.45 2.2 1.75 -0.7 -0.7 0.75 -- --
2)3)4)5)6)
2)3)4)5)7)
Data-out low-impedance time from CK/ tLZ CK Write command to 1st DQS latching transition DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor DQ/DQS output hold time
2)3)4)5)7)
tDQSS tDQSQ tQHS tQH
tCK
ns ns ns
2)3)4)5)
TSOPII
2)3)4)5)
TSOPII
2)3)4)5) 2)3)4)5)
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25
DQS input low (high) pulse width (write tDQSL,H cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Write preamble setup time Write postamble Write preamble
tCK tCK tCK tCK
ns
2)3)4)5)
tDSS tDSH
2)3)4)5)
2)3)4)5)
Mode register set command cycle time tMRD
2)3)4)5) 2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tWPRES tWPST tWPRE
tCK tCK
Data Sheet
18
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
AC Characteristics Table 11 Parameter AC Timing - Absolute Specifications -6/-5 (cont'd) Symbol Min. Address and control input setup time -6 DDR333 Max. -- -- Min. 0.6 0.7 -5 DDR400B Max. -- -- ns ns fast slew rate
3)4)5)6)10)
Unit
Note/ Test Condition 1)
tIS
0.75 0.8
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
0.75 0.8
-- --
0.6 0.7
-- --
ns ns
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tRPRE Read postamble tRPST Active to Precharge command tRAS Active to Active/Auto-refresh command tRC
Read preamble period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Precharge command period Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay
0.9 0.40 42 60 72 18 18 18 12 15
1.1 0.60 70E+3 -- -- -- -- -- -- --
0.9 0.40 40 55 65 15 15 15 10 15
1.1 0.60 70E+3 -- -- -- -- -- -- --
tCK tCK
ns ns ns ns ns ns ns ns
tRFC tRCD tRP tRAP tRRD tWR tDAL
2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
2)3)4)5) 2)3)4)5)11)
tCK
1 75 200 -- -- -- -- 7.8 1 75 200 -- -- -- -- 7.8
tWTR Exit self-refresh to non-read command tXSNR Exit self-refresh to read command tXSRD Average Periodic Refresh Interval tREFI
tCK
ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)12)
tCK
s
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
Data Sheet
19
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
AC Characteristics
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ ns, measured between VOH(ac) and VOL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 12 Parameter
AC Timing - Absolute Specifications -8/-7 Symbol -8 DDR200 Min Max. . Min. -0.75 -0.75 0.45 0.45 -7 DDR266A Max. +0.75 +0.75 0.55 0.55 ns ns
2)3)4)5)
Unit Note/ Test Condition 1)
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time
tAC tDQSCK tCH tCL tHP tCK3 tCK2.5 tCK2 tCK1.5 tDH tDS tIPW tDIPW
- 0.8 - 0.8 0.4 5 0.4 5 8 8 10 10 0.6 0.6 2.5 2.0 - 0.8 - 0.8 0.7 5 -- -- -
+0.8 +0.8 0.55 0.55
2)3)4)5)
tCK tCK
ns ns ns ns ns ns ns ns ns ns ns
2)3)4)5)
2)3)4)5)
min. (tCL, tCH) 12 12 12 12 -- -- -- -- +0.8 +0.8 1.25 +0.6 1.0 7 7
min. (tCL, tCH) 12 12 12 -- -- -- -- -- +0.75 +0.75 1.25 +0.5 0.75 --
2)3)4)5)
CL = 3.0 2)3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5) CL = 1.5 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)6)
7.5 -- 0.5 0.5 2.2 1.75 -0.75 -0.75 0.75 -- --
DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input)
2)3)4)5)6)
Data-out high-impedance time from CK/ tHZ CK Data-out low-impedance time from CK/ CK Write command to 1st DQS latching transition DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor DQ/DQS output hold time
2)3)4)5)7)
tLZ tDQSS tDQSQ tQHS tQH
2)3)4)5)7)
tCK
ns ns ns
2)3)4)5)
2)3)4)5)
2)3)4)5) 2)3)4)5)
tHP -- tQH
S
tHP - tQHS
DQS input low (high) pulse width (write cycle) Data Sheet
tDQSL,H 0.3 --
5 20
0.35
--
tCK
2)3)4)5)
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
AC Characteristics Table 12 Parameter AC Timing - Absolute Specifications -8/-7 (cont'd) Symbol -8 DDR200 Min Max. . DQS falling edge to CK setup time (write tDSS cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input setup time 0.2 0.2 -- -- Min. 0.2 0.2 2 0 0.40 0.25 0.9 1.0 0.9 1.0 0.9 NA NA 0.40 45 65 75 20 20 20 15 15 0.60 -7 DDR266A Max. -- -- -- -- 0.60 -- -- -- -- -- 1.1 Unit Note/ Test Condition 1)
tCK tCK tCK
ns
2)3)4)5)
tDSH
2)3)4)5)
tMRD 2 -- tWPRES 0 -- tWPST 0.4 0.60
0
2)3)4)5) 2)3)4)5)8) 2)3)4)5)9)
tCK tCK
ns ns ns ns
tWPRE tIS
0.2 5 1.1 1.1
-- -- -- -- -- 1.1 1.1 -- 0.60 120E+3 -- -- -- -- -- -- --
2)3)4)5)
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
1.1 1.1
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
Read preamble Read preamble setup time Read postamble Active to Precharge command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Precharge command period Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval Data Sheet
tRPRE tRPRE1.5 tRPRES tRPST
0.9 0.9 1.5 0.4 0 50 70 80 20 20 20 15 15
tCK tCK
ns
CL > 1.5 2)3)4)5) CL = 1.5 2)3)4)5)11)
2)3)4)5)12) 2)3)4)5)
tCK
tRAS Active to Active/Auto-refresh command tRC tRFC tRCD tRP tRAP tRRD tWR tDAL tWTR tWTR1.5 tXSNR tXSRD tREFI
120E+3 ns -- -- -- -- -- -- -- ns ns ns ns ns ns ns
2)3)4)5) 2)3)4)5)
2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
2)3)4)5) 2)3)4)5)13)
(twr/tCK) + (trp/tCK) 1 2 80 -- -- -- -- 7.8 21 1 -- 75 200 -- -- -- -- -- 7.8
tCK tCK tCK
ns
CL > 1.5 2)3)4)5) CL = 1.5 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)14)
200 --
tCK
s
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
AC Characteristics
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V 2) Input slew rate 1 V/ns for DDR400, DDR333, DDR266, and = 1 V/ns for DDR200 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ ns, measured between VOH(ac) and VOL(ac). 11) CAS Latency 1.5 operation is supported on DDR200 devices only 12) tRPRES is defined for CL = 1.5 operation only 13) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
22
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
SPD Contents
5
Table 13
SPD Contents
SPD Codes for HYS64D1600xGDL-[6/7/8]-B HYS64D16000GDL-6-B HYS64D16001GDL-6-B HYS64D16000GDL-7-B HYS64D16001GDL-7-B HYS64D16000GDL-8-B 128MB x 64 1 Rank -8 HEX 80 08 07 0D 09 01 40 00 04 80 80 00 82 10 00 01 0E 04 0C 01 02 20 C1 A0 80 00 V1.2, 2003-08
Part Number & Organization
128MB x 64 1 Rank -6 HEX 80 08 07 0D 09 01 40 00 04 60 70 00 82 10 00 01 0E 04 0C 01 02 20 C1 75 70 00
128MB x 64 1 Rank -6 HEX 80 08 07 0D 09 01 40 00 04 60 70 00 82 10 00 01 0E 04 0C 01 02 20 C1 75 70 00
128MB x 64 1 Rank -7 HEX 80 08 07 0D 09 01 40 00 04 70 75 00 82 10 00 01 0E 04 0C 01 02 20 C1 75 75 00
128MB x 64 1 Rank -7 HEX 80 08 07 0D 09 01 40 00 04 70 75 00 82 10 00 01 0E 04 0C 01 02 20 C1 75 75 00
Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type DDR-I = 07h # of Row Addresses # Number of Column Addresses # of DIMM Banks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] DIMM Configuration Type (non- / ECC) Refresh Rate Primary SDRAM width Error Checking SDRAM width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM CAS Latency CS Latency WE (Write) Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns]
Data Sheet
23
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
SPD Contents
Table 13 SPD Codes for HYS64D1600xGDL-[6/7/8]-B HYS64D16000GDL-6-B HYS64D16001GDL-6-B HYS64D16000GDL-7-B HYS64D16001GDL-7-B HYS64D16000GDL-8-B 128MB x 64 1 Rank -8 HEX 00 50 3C 50 32 20 B0 B0 60 60 00 46 50 30 3C A0 00 00 8F C1 49 4E 46 49 4E 45 4F xx 36 V1.2, 2003-08
Part Number & Organization
128MB x 64 1 Rank -6 HEX 00 48 30 48 2A 20 75 75 45 45 00 3C 48 30 2D 55 00 00 E8 C1 49 4E 46 49 4E 45 4F xx 36
128MB x 64 1 Rank -6 HEX 00 48 30 48 2A 20 75 75 45 45 00 3C 48 30 2D 55 00 00 E8 C1 49 4E 46 49 4E 45 4F 09 36
128MB x 64 1 Rank -7 HEX 00 50 3C 50 2D 20 90 90 50 50 00 41 4B 30 32 75 00 00 9A C1 49 4E 46 49 4E 45 4F xx 36
128MB x 64 1 Rank -7 HEX 00 50 3C 50 2D 20 90 90 50 50 00 41 4B 30 32 75 00 00 9A C1 49 4E 46 49 4E 45 4F 09 36
Byte# 26 27 28 29 30 31 32 33 34 35 41 42 43 44 45 62 63 64 65 66 67 68 69 70 71 72 73
Description tAC SDRAM @ CLmax -1 [ns] tRPmin (ns) tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Bank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] SPD Revision Checksum of Byte 0-62 (LSB only) JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon Module Manufacturer Location Part Number, Char 1
36 - 40 not used
46 - 61 not used
Data Sheet
24
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
SPD Contents
Table 13 SPD Codes for HYS64D1600xGDL-[6/7/8]-B HYS64D16000GDL-6-B HYS64D16001GDL-6-B HYS64D16000GDL-7-B HYS64D16001GDL-7-B HYS64D16000GDL-8-B 128MB x 64 1 Rank -8 HEX 34 44 31 36 30 30 30 47 44 4C 38 42 20 20 20 20 20 xx xx xx xx xx 00 V1.2, 2003-08
Part Number & Organization
128MB x 64 1 Rank -6 HEX 34 44 31 36 30 30 30 47 44 4C 36 42 20 20 20 20 20 xx xx xx xx xx 00
128MB x 64 1 Rank -6 HEX 34 44 31 36 30 30 31 47 44 4C 36 42 20 20 20 20 20 xx xx xx xx xx 00
128MB x 64 1 Rank -7 HEX 34 44 31 36 30 30 30 47 44 4C 37 42 20 20 20 20 20 xx xx xx xx xx 00
128MB x 64 1 Rank -7 HEX 34 44 31 36 30 30 31 47 44 4C 37 42 20 20 20 20 20 xx xx xx xx xx 00
Byte# 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94
Description Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week
95 - 98 Module Serial Number 99 -127 not used
Data Sheet
25
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
SPD Contents
Table 14
SPD Codes for HYS64D32020GDL-[5/6/7/8]-B HYS64D32020GDL-5-B HYS64D32020GDL-6-B HYS64D32020GDL-7-B HYS64D32020GDL-8-B 256MB x 64 2 Ranks -8 HEX 80 08 07 0D 09 02 40 00 04 80 80 00 82 10 00 01 0E 04 0C 01 02 20 C1 A0 80 00 00 50 V1.2, 2003-08
Part Number & Organization
256MB x 64 2 Ranks -5 HEX 80 08 07 0D 09 02 40 00 04 50 50 00 82 10 00 01 0E 04 1C 01 02 20 C1 60 50 75 50 3C
256MB x 64 2 Ranks -6 HEX 80 08 07 0D 09 02 40 00 04 60 70 00 82 10 00 01 0E 04 0C 01 02 20 C1 75 70 00 00 48
256MB x 64 2 Ranks -7 HEX 80 08 07 0D 09 02 40 00 04 70 75 00 82 10 00 01 0E 04 0C 01 02 20 C1 75 75 00 00 50
Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type DDR-I = 07h # of Row Addresses # Number of Column Addresses # of DIMM Banks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] DIMM Configuration Type (non- / ECC) Refresh Rate Primary SDRAM width Error Checking SDRAM width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM CAS Latency CS Latency WE (Write) Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin (ns)
Data Sheet
26
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
SPD Contents
Table 14 SPD Codes for HYS64D32020GDL-[5/6/7/8]-B HYS64D32020GDL-5-B HYS64D32020GDL-6-B HYS64D32020GDL-7-B HYS64D32020GDL-8-B 256MB x 64 2 Ranks -8 HEX 3C 50 32 20 B0 B0 60 60 00 46 50 30 3C A0 00 00 90 C1 49 4E 46 49 4E 45 4F xx 36 34 44 V1.2, 2003-08
Part Number & Organization
256MB x 64 2 Ranks -5 HEX 28 3C 28 20 60 60 40 40 00 37 41 28 28 50 00 00 E5 C1 49 4E 46 49 4E 45 4F xx 36 34 44
256MB x 64 2 Ranks -6 HEX 30 48 2A 20 75 75 45 45 00 3C 48 30 2D 55 00 00 E9 C1 49 4E 46 49 4E 45 4F xx 36 34 44
256MB x 64 2 Ranks -7 HEX 3C 50 2D 20 90 90 50 50 00 41 4B 30 32 75 00 00 9B C1 49 4E 46 49 4E 45 4F xx 36 34 44
Byte# 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Description tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Bank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used SPD Revision Checksum of Byte 0-62 (LSB only) JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon JEDEC ID Code for Infineon Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3
Data Sheet
27
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
SPD Contents
Table 14 SPD Codes for HYS64D32020GDL-[5/6/7/8]-B HYS64D32020GDL-5-B HYS64D32020GDL-6-B HYS64D32020GDL-7-B HYS64D32020GDL-8-B 256MB x 64 2 Ranks -8 HEX 33 32 30 32 30 47 44 4C 38 42 20 20 20 20 20 xx xx xx xx xx 00 V1.2, 2003-08
Part Number & Organization
256MB x 64 2 Ranks -5 HEX 33 32 30 32 30 47 44 4C 35 42 20 20 20 20 20 xx xx xx xx xx 00
256MB x 64 2 Ranks -6 HEX 33 32 30 32 30 47 44 4C 36 42 20 20 20 20 20 xx xx xx xx xx 00
256MB x 64 2 Ranks -7 HEX 33 32 30 32 30 47 44 4C 37 42 20 20 20 20 20 xx xx xx xx xx 00
Byte# 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98
Description Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
99 - 127 not used
Data Sheet
28
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Package Outlines
6
Package Outlines
67.6 63.6 0.1 3.8 MAX.
1.8 0.05
(2.15)
4 0.1
1
18.45 0.1 1.8 0.1 (2.4)
(2.45)
100
31.75
10.1
0.15
11.4 0.1
47.4 0.1
(2.7) (2.45)
4 0.1
1.5 0.1 10.1 101
(2.15) 200
6 0.1 20 0.1
2 MIN. Detail of contacts
0.25 -0.18
0.45 0.03 0.6 0.1
Burnished, no burr allowed
L-DIM-200-006
Figure 4
Package Outlines - Raw Card A DDR-SDRAM SO-DIMM Module HYS64D32020GDL-[5/6/7/8]- B
Data Sheet
2.55
29
V1.2, 2003-08
HYS64D[1600x/32020]GDL-[5/6/7/8]-B Small Outline DDR SDRAM Modules
Package Outlines
67.6 63.6 2.4 MAX.
1.8 0.05
(2.15)
4 0.1
1
18.45 0.1 1.8 0.1 (2.4)
(2.45)
100
31.75
10.1
0.15
11.4 0.1
47.4 0.1
(2.7) (2.45) 1.5 0.1 10.1 101 200 (2.15)
4 0.1
6 20
2 MIN. Detail of contacts
0.25 -0.18
0.45 0.03 0.6 0.1
Burnished, no burr allowed
L-DIM-200-011
Figure 5
Package Outlines Raw Card C DDR SDRAM SO-DIMM Modules HYS64D1600xGDL-[6/7/8]-B
Data Sheet
2.55
30
V1.2, 2003-08
www.infineon.com
Published by Infineon Technologies AG

▲Up To Search▲

Price & Availability of HYS64D16000GDL-8-B

	To Download HYS64D16000GDL-8-B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .